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128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No. 0.1 1.0 History Initial Draft Release Draft Date Jul. 2009 Aug. 2009 Remark Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Aug. 2009 1
Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series DESCRIPTION
The Hynix H57V1262GFR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. H57V1262GFR series is organized as 4banks of 2,097,152 x 16. H57V1262GFR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule)
FEATURES
* * * * Voltage: VDD and VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Ball FBGA (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM * * * * Internal four banks operation Auto refresh and self refresh 4096 Refresh cycles / 64ms Operation temperature HY5V26F(L)F(P)-XX Series: 0 ~ 70oC HY5V26F(L)F(P)-X(I) Series: -40 ~ 85oC * * * * Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency; 2, 3 Clocks Burst Read Single Write operation
This product is in compliance with the directive pertaining of RoHS.
ORDERING INFORMATION
Part No. H57V1262GFR-50X H57V1262GFR-60X H57V1262GFR-70X H57V1262GFR-75X Clock Frequency 200MHz 166MHz 143MHz 133MHz 4Banks x 2Mbits x16 LVTTL 54 Ball FBGA Organization Interface Package
1. H57V1262GFR-XXC Series: Normal power, Commercial Temp.(0oC to 70oC) 2. H57V1262GFR-XXI Series: Normal power, Industrial Temp. (-40oC to 85oC) 3. H57V1262GFR-XXL Series: Low power, Commercial Temp.(0oC to 70oC) 4. H57V1262GFR-XXJ Series: Low power, Industrial Temp. (-40oC to 85oC) Rev. 1.0 / Aug. 2009 2
Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series BALL CONFIGURATION
9 8 7 3 2 1
A B C D E F G H J 54 Ball FBGA 0.8mm Ball Pitch

1
VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS
2
DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5
3
VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4
7 A B C D E F G H J
VDDQ VSSQ VDDQ VSSQ VDD /CAS BA0 A0 A3
8
DQ0 DQ2 DQ4 DQ6 LDQM /RAS BA1 A1 A2
9
VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD
< Top View >
Rev. 1.0 / Aug. 2009
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic & timer CLK CKE State Machine CS RAS CAS WE U/LDQM Row Active
Internal Row Counter 2Mx16 BANK 3 Row Pre Decoder 2Mx16 BANK 2 2Mx16 BANK 1 2Mx16 BANK 0 DQ0 I/O Buffer & Logic Sense AMP & I/O Gate X-Decoder X-Decoder X-Decoder X-Decoder
Refresh Column Active
Memory Cell Array
Column Pre Decoder Y-Decoder
DQ15
Bank Select
Column Add Counter
A0 A1 Address Buffers
Address Register
Burst Counter Pipe Line Control
A11 BA1 BA0
Mode Register
CAS Latency
Data Out Control
Rev. 1.0 / Aug. 2009
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 0 BA0 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
OP Code
A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write
Burst Type
A3 0 1 Burst Type Sequential Interleave
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
Burst Length
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature / Time
Notes: 1. Commercial (0 ~ 70oC) 2. Industrial (-40 ~ 85oC)
Symbol TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER
Rating 0 ~ 70 C -40 ~ 85oC -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 / 10
o
Unit
o o o
Note 1 2
C C C
V V mA W
oC
/ Sec
DC OPERATING CONDITION
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min. 3.0 2.0 -0.3 Typ 3.3 3.0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1, 2 1, 3
Notes: 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration
AC OPERATING TEST CONDITION (VDD=3.30.3V, VSS=0V)
Parameter Symbol Value Unit Note
AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement
Note: 1.
Vtt = 1.4V
VIH / VIL Vtrip tR / tF Voutref CL
2.4 / 0.4 1.4 1 1.4 50
V V ns V pF
Vtt = 1.4V
1
R T = 500
R T = 50
O utput 50pF
O utput
Z0 = 50 50pF
D C O utput Load C ircuit
AC O utput Load C ircuit
Rev. 1.0 / Aug. 2009
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series CAPACITANCE (f=1MHz, VDD=3.3V)
Parameter CLK Input capacitance A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM Data input / output capacitance DQ0 ~ DQ15 Pin Symbol CI1 CI2 CI/O Min 2.0 2.0 3.0 Max 4.0 4.0 5.5 Unit pF pF pF
DC CHARACTERISTICS I
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Notes: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6
Symbol ILI ILO VOH VOL
Min -1 -1 2.4 -
Max 1 1 0.4
Unit uA uA V V
Note 1 2 IOH = -2mA IOL = +2mA
Rev. 1.0 / Aug. 2009
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series DC CHARACTERISTICS II
Parameter Symbol Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS IDD2N Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current IDD3N Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRC tRC(min), All banks active Normal Self Refresh Current IDD6 CKE 0.2V Low power
Notes: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. H57V1262GTR-XXC Series: Normal Power
Speed 5 100 6 80 2 2 7 70 H 70
Unit Note
Operating Current Precharge Standby Current in Power Down Mode
IDD1 IDD2P IDD2PS
mA mA mA
1
18 mA
15 5 5
mA
40 mA
35
IDD4 IDD5
120 210
100 200 2
100 190
100 190
mA mA mA uA
1 2
800
3
H57V1262GTR-XXL Series: Low Power
Rev. 1.0 / Aug. 2009
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter CL = 3 CL = 2 Symbol tCK3 tCK2 tCHW tCLW CL = 3 CL = 2 tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 5 6 7 H Unit Note ns ns 5.4 6.0 5.4 6.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 2
Min Max Min Max 5.0 1.75 1.75 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 1000 4.5 4.5 6.0 2.0 2.0 2.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.0 1000 5.4 5.4 -
Min Max Min Max 7.0 2.0 2.0 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 1000 5.4 5.4 7.5 10 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 1000
System Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Access Time From Clock Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time
CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time
Notes:
CL = 3 CL = 2
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter RAS Cycle Time RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z CL = 3 CL = 2 Operation Auto Refresh Symbol tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF 2 0 2 3 1 1 64 2 0 2 3 1 1 64 5 Min 55 55 15 38.7 15 10 1 0 2 Max 100K Min 60 60 18 42 18 12 1 0 2 6 Max 100K Min 63 63 20 42 20 14 1 0 2 tDPL + tRP 2 0 2 3 1 1 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1 7 Max 100K Min 63 63 20 42 20 15 1 0 2 H Max 120 K Uni t ns ns ns ns ns ns CLK CLK CLK Not e
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note:
1. A new command can be given tRRC after self refresh exit.
Rev. 1.0 / Aug. 2009
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series COMMAND TRUTH TABLE
Command Mode Register Set CKEn-1 H CKEn X CS L H No Operation H X L Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit L H L H Entry Precharge power down Exit L H L H Entry Clock Suspend Exit L H H L L V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X H H H H H H X L L L L H X L H X L L L X L L L X H L H X X H L X V X X X X X L L H L X X L X X X A9 ball High (Other balls OP code) MRS
Mode
RAS L X H L
CAS L X H H
WE L X
DQM X
ADDR
A10/AP OP code
BA
Note
X H H X RA
X
H
X
L
V L
X
L
H
L
H
X
CA H L
V
X
L
H
L
L
X
CA H H
V
X V
Rev. 1.0 / Aug. 2009
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series PACKAGE INFORMATION 54 Ball FBGA 8.0mm x 8.0mm
8.00 Typ. 6.4 0.80.1 A1 INDEX MARK Unit [mm]
0.80 Typ.
8.00 Typ.
Bottom View
6.4
0.45 +/- 0.05 0.35 +0.025/- 0.05
0.8 0.1 1.60 0.80 Typ.
1.0 max
Rev. 1.0 / Aug. 2009
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